This page contains the high level schematics of the Random Clock project at the surface level. For in-depth explanation of each sub module, use the Design tab.

Schematics

Fig 2. Overall System Block Diagram

The MCU generates a random array of numbers from 1 to 12 depicting where each number will go on the clock panel each hour. This information is sent to the FPGA by SPI. The FPGA uses a shift register to receive the information, and decodes it into a format suitable for the seven-segment displays. The MCU also takes the random array and encodes it into servo positions for the minute and hour hand, telling them where to turn as time passes. For greater details of the designs, visit the “Design” tab of the website.

Fig 3. Physical Circuit Diagram

Fig 4. Pinout Chart

All signals labeled in Fig 3. can be found on Fig 4 when connecting the system together. The FPGA signal names are also contingent with the corresponding .sv files. The decoder block in Fig 3. is a physical module, with its schematics provided in Fig 5.

Fig 5. Decoder Circuit Diagram

The decoder module uses 3 physical decoder IC’s as well as some AND, NOT gates to decode the 5 bit signal (en [4:0]) describing which LED display to enable. The output of the decoder module are 24 physical wires that connect to each seven-seg display’s common anodes. In hindsight, this was unnecessary since the FPGA has 48 I/O pins, meaning without the physical decoding modules, we would only have used 36 of them. With the decoder module, we cut down this number to 17, freeing up more pins for further implementations should we choose to do so.

Source Code Overview

The source code for the project is located in the Github repository here.